This invention relates to a substrate having a dielectric film thereon, methods of depositing the dielectric film on the substrate, and to associated devices.
Many devices are fabricated by building up multiple thin dielectric, semiconducting and metal layers on a substrate such as a silicon wafer. However, the deposition of these layers results in a build-up of stress. The net stress produced at each stage places constraints on subsequent process steps. For example, the net stress imparted can result in warpage of the wafer, which can ultimately result in wafer loss due to handling problems. A further problem is cracking of the layers which in turn results in a reduction in yield and wafer loss. The net stress that the wafer is subjected to may be a tensile stress or a compressive stress.
It is standard practice in semiconductor wafer fabrication to attempt to minimise wafer warpage. It is also standard practice to attempt to deposit layers without cracks. In order to minimise wafer warp, it is known to reduce the internal stress within a deposited film to an acceptable level by a treatment such as ion bombardment or process chemistry. Alternatively, layers may be selected to compensate for the stress in underlying films. For example, it is known to deposit a film which is subject to a compressive stress on top of a film that is subject to a tensile stress. However, these prior art techniques have their limitations. Typical methods employed to control stress within a film are the plasma conditions which influence net growth rate such as deposition rate and RF bias, the intrinsic properties of the material selected, deposition temperature and thickness of the film. However device design places constraints on many of these parameters and as a consequence of these constraints novel processes are required to deliver some new advanced devices.
Further problems are encountered in the manufacture of high power, high voltage capacitor devices. Devices of this kind commonly require polyimide to be integrated into the device. Whilst polyimide offers many benefits, there are some undesirable constraints associated with the use of this material. Typically, the thickness of the deposited polyimide film is limited to less than 10 microns. This in turns limits the voltage and hence the electric field that can be applied to the device. Also, polyimide has a relatively low thermal budget. The cure temperature of polyimide is 280° C. As a result, any dielectric isolating layers must be compatible with this temperature restraint. Effectively, this means that the temperature associated with the deposition of isolating layers should not exceed 280° C. Commonly, silicon dioxide is used as the isolating layer.
There is a requirement to operate future devices at higher voltages than can be achieved currently. It would be highly desirable to provide silicon dioxide isolation layers which have a thickness of 20 microns or greater in order to cope with the requirements of new devices that may utilise polyimide. However, it is currently not possible to deposit such thick, homogeneous layers of silicon dioxide at temperatures of 280° C. or lower. This is because the layers crack due to the build-up of stress in the film.